This invention relates to a digital phase-locked loop system in which a phase-locked loop (PLL) constructed with digital circuit elements.
Many types of digital phase-locked loop systems have been recently disclosed. These digital phase-locked loop systems have a phase-locked loop composed of digital circuit elements. In comparison with analog type systems, such digital type systems have advantages for example, that scatter due to parts used is insignificant and that desired characteristics can be obtained without the necessity of adjustment. On the other hand one problem, in digital phase-locked loop systems is that, an output from a stationary oscillator is frequency-divided and outputted as an output from the loop, and therefore the phase-locked loop can be operated only by input frequencies in the range below one several-tenth of a maximum frequency for operating a logical circuit element incorporated therein.
Furthermore another problem is that, if the input frequency is increased, a frequency-dividing rate becomes smaller, resulting in rougher quantization and worse loop characteristics. Especially in digital phase-locked loop systems utilizing input frequencies in the range of a fraction of a highest operating frequency of the logical circuit element, influence of characteristics of the logical circuit element itself, especially influence of delay characteristic, is significant as well as the influence of the quantization error and thus, adoption of a complicated circuit composition is difficult.
FIG. 21 shows an example of a traditional phase-locked loop system for the input of a fraction (1/N, N: a positive integer) of a frequency of a traditional stationary oscillator (OSC) 4. Phase difference between input signal PBSG and phase-locked loop clock signal PLLCK is detected as counted value of a counter 1.
Clock pulse MCK which is an output of the stationary oscillator 4 is shown in FIG. 22 (1), input signal PBSG in FIG. 22 (2), and phase-locked loop clock signal PLLCK in FIG. 22 (3). Signal QA from an output terminal Q of the D-type flip-flop 3 is shown in FIG. 22 (4). Clock pulse MCK, input signal PBSG, and output signal QA of a D-type flip-flop 3 are applied to an AND gate G1 and an output of the AND gate G1 is supplied to a clock input terminal CK of the counter 1. Output signal CNTOUT of the counter 1 is shown in FIG. 22 (5).
Output signal U of a frequency divider 7 is applied to a clock input terminal CK of a D-type flip-flop 8 and is also applied to the clock input terminal CK of the D-type flip-flop 3 through an inversion circuit N1 and then drawn out as phase-locked loop clock signal PLLCK.
Output of an AND gate G2 is applied to the counter 1 and register 5 as reset signal RESET. The reset signal RESET is as shown in FIG. 22 (6). In FIG. 22, there exists a phase difference in the time interval between a step-up edge "a" of the input signal PBSG and a step-up edge "b" of the phase-locked loop clock signal PLLCK and this time interval is counted by the counter 1.
The input signal PBSG, output signal QA from the D-type flip-flop 3 which latches the input signal PBSG at the step-up or leading edge of the phase-locked loop clock signal PLLCK, and clock pulses MCK from the stationary oscillator 4 are applied to the AND gate G1 before the clock input into the counter 1, by which the counter 1 provided with the output of the AND gate 1 counts the time between the edges a-b. The counter 1 counts the pulses from the AND gate G1 until reset signal RESET from the other AND gate G2 is inputted.
Output from a terminal Q of the D type flip-flop 8 which latches the output from a terminal Q of the D type flip-flop 3 at the step-up edge of the signal U and the output from the terminal Q of the D type flip-flop 3 are applied to the AND gate G2 and the signal CNTOUT which represents the counted value of the counter 1 is latched by the register 5 at the step-up edge of the reset signal RESET from the AND gate G2.
Then the counter 1 is reset in response to the reset signal RESET and set at the step-up edge the next input signal PBSG, and the next counting operation is started. Phase difference signal I outputted from the register 5 is shown in FIG. 22 (7), which is applied to a decoder 6 and decoded. Load signal E outputted by the decoder 6 is as shown in FIG. 22 (8), which signal is loaded in the frequency divider 7 as a frequency dividing rate for the frequency divider 7.
In this way, the clock pulse MCK from the stationary oscillating circuit 4 is frequency-divided by a value represented by the phase difference signal I indicative of the difference between the input signal APBSG and phase-locked loop clock signal PLLCK, and then a frequency dividing rate of the frequency divider 7 generating the phase-locked loop clock signal APLLCK is changed to another one, so that phases of the input signal PBSG and phase-locked loop clock signal PLLCK are kept so as to agree with each other.
The frequency dividing rate of the frequency divider 7 is N when the phases of the input signal PBSG and phase-locked loop clock signal PLLCK agree, and the rate becomes N+1 or N-1 depending on the degree of the phase difference so that the phases agree with each other. For instance, the decoder 6 at N=8 functions to decode to load signal E for the frequency divider 7 to obtain the frequency dividing rate of the frequency divider 7 corresponding to the phase difference signal I.
The frequency divider 7 is loaded with the load signal E representing the frequency dividing rate applied from the decoder 6 in response to load clock signal F. This load clock signal F is generated as shown in FIG. 22 (9) by the logical circuit 9 when the output signal U of the frequency divider 7 represents a specified value. In FIG. 22, where N=8, and since phase difference exists between the time points a and b, load signal E representing frequency division into 9 is applied to the frequency divider 7 from the decoder 6 at the time point c, and the phase difference is corrected to zero at the time point d.
According to the prior art as shown in FIGS. 21 and 22, when the input signal APBSG has a constant cycle as shown in FIG. 22, a normal operation is possible. However, when the input signal PBSG has a modulated waveform as shown in FIG. 23 (1), the cycle of the input signal PBSG changes to longer or shorter one. The phase-locked loop clock signal PLLCK at this time is shown in FIG. 23 (2). When phase difference is caused to it, it may be corrected by the length of the cycle of the input signal PBSG.
FIG. 23 (3) shows the output signal QA of the D type flip-flop 3, FIG. 23 (4) shows the output signal CNTOUT of the counter 1, FIG. 23 (5) shows the reset signal RESET, FIG. 23 (6) shows the phase difference signal I outputted by the register 5, FIG. 23 (7) shows the load signal E representing a frequency dividing rate of the decoder 6, and FIG. 23 (8) shows the load clock signal F from the logical circuit 9. In FIG. 23, the phase difference at the point of time al is corrected at the points of time b1, c1, and d1 in the same way and therefore the phase becomes reversed in polarity at the point of time b1 which gives adverse influence on the phase-locked loop characteristics.